Advanced Microcontroller Bus Architecture is generally defined as an open standard; on-chip communication standard and an on-chip interconnect specification for the development, management and connection of blocks in a design. While considering the design issues, a multi-processor design faces many problems. AMBA as an architecture facilitates the development of these designs eventhough they have large numbers of controllers and peripherals. AMBA is used as the on-chip bus in System on chip designs (SoCs), Application Specific Integrated Circuits (ASICs) and High Level Embedded Microcontroller.
AMBA was first introduced in the year 1996.It is a registered trademark of the company ‘ARM Limited’. The current versions of Advanced Microcontroller Bus Architecture include AMBA1 or AMBA , AMBA2, AMBA3, AMBA4 and AMBA5.The main objectives of AMBA versions are; allow right first time development, be technology independent, encourage a modular system design and efficiently reduce the silicon infrastructure. Through these objectives; AMBA versions can help in design reuse, can act as bus with high speed and high bandwidth thereby helping in the improvement of system performance. Testing Methodology feature in all the AMBA versions helps in testing and diagnosis of designs.
AMBA1: Introduced in the year 1996, AMBA1 had only two buses named Advanced System Bus (ASB) and Advanced Peripheral Bus (APB). It was the first version introduced by ARM.
AMBA2: The second version of AMBA came out in the year 1999 with a new bus named Advanced High Performance Bus (AHB) along with ASB and APB.
AMBA3: Third generation of AMBA was brought out in the year 2003. Through this version ARM introduced Advanced Extensible Interface (AXI3 or AXI v1.0).With slight modifications in AHB and APB, AHB – Lite v1.0 and APB3 v1.0 came out respectively. Advanced Trace Bus (ATB v1.0) was introduced to allow on-chip debug and for trace solution.
AMBA4: In the year 2010, the fourth generation of AMBA came out with a new bus named AXI Coherency Extensions (ACE).With slight changes; AXI4, AXI4-Lite, AXI- Stream v1.0, ATB v1.1, APB4 v2.0 and ACE- Lite were introduced.
AMBA5: AMBA 5 CHI (Coherent Hub Interface) specification was introduced by ARM in the year 2013 to enable high performance and scalable system on chip technology. It supports non-blocking coherent data transfers between processors using caches. This is used by Cortex-A57, Cortex-A53 processors, CoreLink DMC-520 Dynamic Memory Controller and CoreLink CCN-504 Cache Coherent Network.
Inorder to reduce the complexity due to interfacing and power consumption; Advanced Peripheral Bus is used in AMBA based designs. Low bandwidth peripherals are interfaced by using APB. Through APB, system performance can be improved in terms of operation and integration. APB Bridge and APB Slave are the two main components of this bus. APB Bridge is the bus master. Only one bus master will be there for the APB in AMBA based designs.
The main functions of APB Bridge are address latching, generate a strobe signal PENABLE and select signal PSELx, put the data on APB for write transfer and also allow the APB data to be available for read transfer. Many timing parameters are related to APB Bridge. These parameters are classified as input and output parameters. Interfacing of the APB Slave is said to be very flexible and simple. Similar to the APB bridge timing parameters are there to control the APB Slave operation.
The basic signals that aid the operation of APB are PCLK, PRESETn, PADDR [31:0], PSELx, PENABLE, PWRITE, PRDATA and PWDATA. APB3 v1.0 is a subset of APB. Here two extra signals PREADY and PSLVERR are used along with the other signals of APB. APB4 v2.0 is the latest improved version of APB.
As a high performance pipelined bus, ASB can be used in the design of many embedded microcontrollers. It supports the connection of many processors, external memory interfaces and on-chip memories. The main features like burst transfer, multiple bus master support and better pipelined operation can be obtained through ASB.
The main components of ASB are ASB Master, ASB Slave, ASB Arbiter and ASB Decoder. ASB Master initiates the write and read operations through address and control information. Many bus masters are present in ASB; but at a time only one of them will get access. ASB Arbiter will help the master to achieve access to ASB. The main function of ASB Slave is to respond to the read and write operations. For decoding the address and to select the appropriate slaves ASB Decoder is used.
Non-Sequential, Sequential and Address-only are the three main types of transfer that can take place through ASB. The different signals used in this bus are DSELx, BWRITE, BWAIT, BTRAN [1:0], BPROT [1:0], BSIZE [1:0], BnRES, BLOK, BLAST, BERROR, BD[31:0], BCLK, BA[31:0], AREQx and AGNTx.
AHB is generally a high performance bus which can provide better bandwidth operation. Through AHB, a design can achieve features like split transactions, better data bus configuration, burst transfer, single clock edge operation etc. AHB is used on ARM7, ARM Cortex-M and ARM9 based designs. AHB system design contains AHB master, AHB Slave, AHB Decoder and AHB arbiter.
AHB master helps in read and write operations through address and control. AHB system design may contain more than one master. At one time, only one of master can use the bus efficiently. AHB Slave responds to the AHB Master. With the help of the address; slave responds to the read or writes operation. The status of the data transfer is acknowledged by the slave to the master. Status means whether the data transfer was a success, failure or a wait. AHB Arbiter and AHB Decoder have functions similar to ASB.
AHB signals are HWDATA [31:0], HSELx, HRDATA [31:0], HREADY, HRESP [1:0], HSPLITx [15:0], HMASTLOCK, HMASTER [3:0], HGRANTx, HLOCKx and HBUSREQx. AHB-Lite v1.0 supports a single master and provides a better bandwidth operation. Other than the basic AHB signals, this version uses other signals also; for better operation.
AXI v1.0, a burst based protocol, was first introduced by ARM in the third generation of AMBA. It provides better performance, high frequency and high speed operation. Here there is a separate address and data phase. It supports data transfers using byte strobes. Here burst transactions are possible with only start address issue. Ability to give multiple addresses helps AXI to be more useful.
Global signals, write data channel signals, write address channel signals, write response channel signals, read address channel signals, read data channel signals and low power interface signals are the different categories of signals present in AXI. Five Separate channels are present to allow the read and write operation. Out of order transaction completion and addition of register stages are the other main features of AXI. AXI4 – Lite is an improved subset of AXI. It modifies the signals of the basic AXI. This subset uses a fixed data bus width and supports write strobes. AXI- Stream v1.0 is the latest version of AXI.
ACE is an extension to the AXI with enhancements like third level caches, on-chip RAM, peripherals and external memory. Here, the width of the AXI read and write channels can be configured for a 64-bit or 128-bit interface. It supports 1:1 clock ratios with respect to the processor clock. It can also run, at any multiple of the processor clock. ACE is used on the ARM Cortex-A processors like Cortex-A7 and Cortex-A15.The different components in ACE are Interconnect, ACE Masters, ACE – Lite Masters and ACE- Lite /AXI slaves. ACE provides a framework for system level coherency. Read Data Channel Signals, Read Address Channel Signals, Snoop Channel signals, Write Address Channel Signals and Response signals are the major signals categories of ACE.
ACE-Lite is a subset of ACE. ACE-Lite is used by master components that do not have hardware coherent caches. They can indicate whether the issued transactions could be held in the hardware coherent caches of other masters and also they will help in barrier transactions. It consist additional signals on the read address channel and write address channel. ACE-Lite does not include snoop channels, snoop signals and response signals.
Advanced Trace Bus (ATB) facilitates transfer of trace data around the CoreSight debug system. Using valid and ready responses, stalling of data is possible. It supports byte-sized packets and the control signals used indicate the number of bytes valid in each cycle. ATCLK, ATCLKEN, ATRESETn, ATVALID, ATREADY, ATID [6:0], ATBYTES [m:0], ATDATA [n:0], AFVALID and AFREADY are the signals used by this bus for operation.
SDRAM and Flash memory controllers (DMC-34x), Network Interconnect (NIC-301), cache controllers (L2C-310), DMA controllers (DMA-230 etc. makes use of AMBA. Non-ARM designs also use AMBA.
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