Introduction- Hardware Description Language

Hardware description language or HDL helps to describe the structure and behavior of electronic circuits.  It helps in the synthesis of HDL description into the netlist. This is placed, routed and produced so that the set of masks create an IC.

HDLs form an integral part of electronic design automation (EDA) systems, especially for complex circuits, such as  microprocessors, application-specific integrated circuits, and programmable logic devices.


hdl design flow

            Figure 1: HDL Design Flow

The HDL design flow consists of 5 important steps.

  • Design Entry

In this step, the design is converted to a machine readable format. In here, we will be using a computer aided design tool. This CAD tool supports many design entry methods like schematic capture, HDL entry, netlist.

  • Functional Simulation

Once a design has been captured, the next step is to simulate it. This is done to ensure that the design will meet the requirements of its specification. The first type of simulation that is performed is a Functional Simulation. This is also referred to as a Behavioral simulation in Xilinx Foundation.

A behavioral simulation helps to verify the logical behavior of the circuit. It helps in the realization of simulations which contains the physical implementation. It does not include any of the timing information.

  • Synthesis

During the synthesis purpose, the CAD will be interpreting the VHDL design information and building blocks which implements design. Many differences in the VHDL description results in different hardware.

  • Device configuration

After the design has been verified, a binary hardware configuration file is generated (bitstream). This file is then downloaded into the FPGA via the JTAG interface.

What is VHDL???

VHDL is an acronym for Very High Speed Integrated Circuit Hardware Description Language. This HDL can be used to model a digital system at different levels of abstraction which ranges from algorithmic to gate level.

VHDL language is an integration of different languages like:

  • Sequential language
  • Concurrent Language
  • Net-list language.
  • Timing specifications
  • Waveform Generation language.

Structure of VHDL

VHDL is used to describe the model of a digital hardware. This model gives the external view and one or more internal views.

  • Internal View: Gives the functionality of the structure.
  • External view: Gives the interface of the device.

VHDL provides 5 different primary constructs called design units. They are:

  1. Entity declaration
  2. Architecture body
  3. Configuration declaration
  4. Package declaration
  5. Package body.


Entity is modeled using the entity declaration and architecture body. Entity declaration tells about the external view of the entity. That is, it tells about the input and output signal names. While the architecture body consists of the internal description of the entity.

Consider a half adder circuit below:

The entity of the half adder circuit is:

half adder


                                Figure 2: Entity

Here A and B is the input port. S and C is the output port.

Architecture Body

Internal details of the entity are specified by the architecture body using the below modeling styles:

  • As a set of interconnected components.
  • As a set of concurrent assignment statements
  • As a set of sequential assignment statements
  • Combination of any three.

common vhdl types

                                          Figure 3: Common VHDL Types

Basic Language Elements


There are basically two types of identifiers in VHDL.

  • Basic Identifiers
  • Extended Identifiers

Basic Identifiers

Basic identifiers are basically characters. The character must be a lowercase letter, uppercase letter, a digit or any underscore character.  Here the first character must be a letter, a last character must be not a underscore.

Some examples of basic identifiers are DRIVE_BUS, SET_CK_HIGH etc.

Extended Identifier

It is a sequence of characters written between two backslashes.  Here any of the characters can be used like the @, $, %,

Some examples are:




Comments are represented by (--).


 -- a&b;

-- this is an or gate program


Keywords are reserved words that are used in VHDL.

Data Objects

A data object holds a value of a specified type. It is created by means of an object declaration.

 An example is:

 variable COUNT: INTEGER;

Each of the data object belongs to one of the classes:

  1. Constant

Any object that has constant class holds a single value of a given type. Before the simulation process starts, the value is being assigned to the object and this value cannot be changed while the simulation process takes place.

  1. Variable

A data object of variable class holds a single value of a given type. Here different values can be assigned to the object at different times using the variable assignment statement.

  1. Signal

An object that belongs to the signal class has history of values, and a set of future values. Future values are assigned to the signal object by using the signal assignment statement.

Object Declaration

There are different ways by which we can declare an object.

  1. Constant Declaration
 constant Rise_time: time=50ns;

The type of declaration means that the object Rise_time can hold a value of the type time. The time of simulation starts with a time of 50ns.

  1. Variable Declaration
? variable ctrl: bit vector (10 downto 0);

This variable declaration includes a variable ctrl which has an array size of 11. Each value in the array will be a bit.

  1. Signal Declarations
signal clock: bit;

This declaration defines a signal clock holding a bit with initial value zero.

Data Types

All data objects in VHDL holds a value which belongs to a set of values. These set of values is specified with the help of data types. A type is a name which is associated with a set of values and set of operations.

The different data types are:

  • Subtypes
subtype MY_INTEGER is INTEGER range 48 to 156;

type DIGIT is ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9') ;

From the above examples,

MY_INTEGER is the subtype of the base type INTEGER. The INTEGER ranges from 48 to 156. In the second example, the DIGIT is defined as an enumeration type. 

Thus, a subtype is a type with a constraint.  Here the constraint defines the subset of values for the type.

  • Scalar Types

Scalar types are classified into 4 types. They are:

  • Enumeration.

This a scalar data type where it has a set of user-defined values which consist of character and identifier literals.  Some examples are:

Type month is ('Jan’, ‘Feb’, ‘Mar’, ‘Apr’, ‘May’, ‘Jun’, ‘Jul’, ‘Aug’, ‘Sep’, ‘Oct’, ‘Nov’, ‘Dec’);

  • Integer

A integer is another scalar data type whose set of values fall within a specified data range.

For example:

type SEL is range 0 to 15;

In this example; the SEL is an integer array with array size of 16.  Each array will be handling a integer value.

  • Physical

A physical type has values that represent the measurement of physical quantity.

 type VOLTAGE is range 0 to 1E6 units

 mV; --  0.001 V – millivolt.

 uV = 1E-6; -- microvolt.

 MV = 1E6 V ; --megavolt.

end units;
  • Floating Point

A floating point data type is a scalar data type which has a set of values in the range of real numbers.


type VOLTAGE is range -5.5 to -1.4;

The example shows that the type VOLTAGE ranges from -5.5 to -1.4. Here voltage represents a floating data type.

  • Composite Types

Composite types represent a collection of values. There are two classes of composite types: arrays containing elements of the same type, and records containing elements of different types.

  • Array Types

An object of an array type consists of elements that have the same type.

One example is:

type ADDRESS_WORD is array (0 to 63) of BIT; 
  • Record Types

An object of a record type is composed of elements of same or different types.

An example of a record type declaration is

type PIN_TYPE is range 0 to 10;

type MODULE is


SIZE: INTEGER range 20 to 200;




end record;
  • Access Types

Values belonging to an access type are pointers to a dynamically allocated object of some other type.

 type PTR is access MODULE;

 type FIFO is array (0 to 63, 0 to 7) of BIT;

 type FIFO_PTR is access FIFO;
  • Incomplete Types

An incomplete type declaration has the form

 type type-name;


The five different types of operators are:

  • Logical

The commonly used 6 logic operators are:

and    or    nand    nor    xor    not

These operators are defined for the types BIT and BOOLEAN. 

  • Relational

The relational operators are

   =       /=       <       <=       >     >=

The result types of all these relational operators are BOOLEAN.

  • Adding

These are

                      +  -  &

      +    :  ADDITION


      &   :  CONCATENATION

  • Multiplying

  These are   * / mod rem.

  • Miscellaneous

The miscellaneous operators are

        abs     **

The abs (absolute) operator is defined for any numeric type.

The ** (exponentiation) operator is defined for the left operand to be of integer or floating point type and the right operand (i.e., the exponent) to be of integer type only.

VHDL Modeling Types

Dataflow modelling

A dataflow model specifies the functionality of the entity without explicitly specifying its structure. This functionality shows the flow of information through the entity,

  • What is concurrent signal assignment in dataflow modeling?

The dataflow behavior in the entity is described with the help of concurrent signal assignment (<=).

Example: Z <= A or B.

  • Difference between concurrent versus sequential assignment statement?

Signal assignment statements can also appear within the body of a process statement. Such a statement is known as sequential assignment statement. But signal assignment statements that come outside the process is called as concurrent signal assignment statements.

  • Example of Data flow modelling

Consider a 4:1 multiplexor.

mux dataflow

                                Figure 4: Multiplexor 

Step1: In data flow modelling, we analyze the circuit in the form of equations.  So, before entering to the programming part the 4:1 mux is realized in equation form.

The 4:1 mux consists of four inputs A, B, C, D and select lines a, b. The output of the mux is Q.

Here Q= (abar. b bar. A) + (abar .b .B) + (a .b bar .C) + (a .b .C).

Step2:  After realizing the equations, the next step is to do the programming part.

In the program,


mux dataflow output

                                                   Figure 5: Multiplexor Program and Simulation

First: Entity is declared.

Inputs are declared. The in resembles the inputs of the 4:1 mux. The out resembles the outputs of the mux.

Second:  Architecture body is defined.

Here r and s resembles not part of the gates.  r, s are defined in the program as signals.  Then Q is defined.

Think & Learn:    Design a full adder using NAND Gate?????

                       Design universal logic gates?????

Behavioral modeling

In this modeling style, the entity behavior is done by sequential execution, procedural type code similar in semantics and syntax to that of a programming language like C.

  • How to declare an entity in behavioral modeling?
       entity entity-name is

       [ generic ( list-of-generics-and-their-types ); ]

       [ port ( list-of-interface-port-names-and-their-types) ; ]

       [ entity-item-declarations ]

       [ begin


       end [ entity-name ];
  • How to declare an architecture body in behavioral modeling??

  • What is a Process Statement in Behavioral Modeling?

A process statement contains sequential statements that describe the functionality of a portion of an entity in sequential terms. The syntax of a process statement is

  • How to assign a variable in behavioral Modelling?

Variables are usually used inside the process statement. The format is:

variable-object := expression;
  • How to do signal declaration in behavioral modelling?

Signals are assigned values using a signal assignment statement The simplest form of a signal assignment statement is

signal-object <= expression [ after delay-value ];
  • IF Statement

  • CASE Statement

The format is:

case expression is

       when choices => sequential-statements -- branch #1

       when choices => sequential-statements -- branch #2

       [ when others => sequential-statements ] -- last branch

       end case;

Programming Example:  4:1 MUX in behavioral modelling.

In behavioral modelling, the multiplexor is programmed by considering its truth table.

So, for a 4:1 mux the truth table is:

multiplexor behavioral       mux behavioural truth table 

                      Figure 6: Multiplexor Diagram and Truth table

Now its program:

mux behavioural program

mux behavioural simulation

                                    Figure 7: Multiplexor Program and Simulation

Think & Learn:  Design a 4x3 ROM Memory?

                              Design a barrel shifter?

                              Design shift registers?

Structural modelling

An entity is modeled as a set of components connected by signals, that is, as a netlist. The behavior of the entity is not explicitly apparent from its model. The component instantiation statement is the primary mechanism used for describing such a model of an entity.

Programming Example: 4:1 multiplexor

In structural modelling, the architecture of 4:1 mux is being considered.

mux structural

                                                      Figure 8: Multiplexor 

First: Entity is declared.

Second:  architecture is defined. In the architecture, the mux 2 to 1 is defined as component.

  • How to declare a component in Structural Modelling?

The syntax of a simple form of component declaration is

component component-name 

port ( list-of-interface-ports ) ;

end component
  • How to perform component instantiation?

A format of a component instantiation statement is

component-label: component-name port map ( association-list) ',

Third:  the program uses the method of component instantiation, where the function port map is being used. 



                                 Figure 9: Multiplexor  Diagram and Simulation

Think & Learn Design a ripple carry adder?

                        Design a full adder using 8x1 multiplexor?

                              Design a gray to binary code convertor using encoder?