Programmable Logic Device

PLDs are semiconductor devices that can be programmed to obtain required logic device. Because of the advantage of re-programmability, they have replaced special purpose logic devices like Logic gates, flip-flops, counters and multiplexers in many semicustom applications. It reduces design time and thus reduces time for the product to reach the market.  It consists of arrays of AND and OR gates, which can be programmed to realize required logic function.

Device programmer blows fuses on the PLD to control each gate operation. Inexpensive software tools are used for quick development, simulation and testing, therefore design cost is comparatively low. Another important advantage is that customer can modify their design, based on changes in requirement. 

The most commonly used Programmable Logic Devices are listed here

(a). Programmable Read Only Memory

Programmable read only memory is a memory chip, on which data can be written only once. Once a data is written onto a PROM, it remains there forever. Therefore, it is also called as a one-time programmable memory. Memory chip is delivered blank and the programmer transfers the data on to it. A blank PROM consists of many fuses which can be selectively burned out during the first programming. They are used in applications like, computer bios where reprogramming is not required.

PROM

The above figure shows the block diagram of a PROM. It consists of a fixed AND gate array followed by a Programmable OR gate array. AND gate array is used as the address decoder which selects the corresponding address location based on the input address provided to it. Data is stored in the OR gate array. It contains programmable fuses, which can be burned off depending on the data values that are to be stored.

Internal Structure of PROM

Internal structure of each block in the PROM is shown in the above figure. Here, A and B are the address inputs and Y is the data output. AND arrays are fixed to select each row (address location) for corresponding inputs. As shown in the figure, data in each memory location is determined by the fuses in the OR array. If the fuse is not burned off, charge send through the row is received at the output, indicating a logic one and when the fuse is burned off, the signal cannot reach the data output and is detected as logic zero. Thus, in PROM binary data is stored using fuses. 

For example in this PROM, single bit data can be stored in each memory location (fuses). Since there are four address locations to store data, two bit address inputs are required to select these locations. Working of a PROM can be better understood if it is explained with an example. Consider address input to be “00”. As shown in the above figure, the inverted values of both address inputs are given to the first AND gate. That is, both inputs of first AND is now at logic one. This means that, first address location is selected. Now, data in the first address location is determined by the presence or absence of fuses in the OR array. Like in above figure, if fuse at this location is burned off, then, output data is ‘0’. Similarly in this example, logic one is stored in second and third location and logic zero in the fourth location.

Programmable Read Only Memory as Logic Device

Programmable Read Only Memory can also be used as a logic device. A logic device performs an operation on one or more inputs, and produces a single output. Output is constant for respective input combinations. Therefore, if the device behavior is stored, the PROM can work like a logic device.

For this, address pins of the PROM are used as the inputs of the logic device and data out is same as PROM output data. Outputs of respective inputs are stored in the corresponding memory locations. For example an XOR gate can be implemented by storing its output values in the respective address location. 

Address Data
00 0
01 1
10 1
11 0

We know that, output of a two input XOR gate is logic one, if exactly one of its input is at logic one state. The table shows a two bit PROM with four address locations (‘00’, ‘01’, ‘10’, ‘11’) in which data ‘0’, ‘1’, ‘1’, and ‘0’ are stored. Therefore, if input is ‘00’ (address input for PROM) the data (‘0’) stored in the memory location ‘00’ is fetched and outputted. Similarly, we get logic one at the output for the input combinations ‘01’ and ‘10’ and logic zero for ‘11’. Thus device works like a two input XOR gate. Any other two input logic device can be implemented using this PROM by changing the data stored in the memory. Now refer the figure of the example that was discussed earlier.

If there are m address bits, then 2^m locations can be addressed with that. This 2^m address locations can store 2^(2^m) different values, therefore 2^(2^m) logic function can be implemented using an m bit PROM.  In our example, we used a simple PROM with two address bits. That means, 2 ^ 2 data can be stored in it. Each data combination is a particular logic function. 

(b). Programmable Array Logic (PAL)

PAL or Programmable Array Logic is used to implement logic functions in digital circuits. Structure of a PAL can be divided into two parts, AND and OR array. In this, AND array is programmable that means connections to the inputs of each AND gate is through fuses. Therefore, when a particular input is not required to implement, using a specific logic function, it can be burned off. AND array is followed by a fixed OR array. It is used to sum off outputs from all AND gates. Input connections are fixed in the OR gate array, therefore, no changes can be made in this section of PAL device.

                                Fig 1: Block Diagram of Programmable Array Logic

Internal structure of a two input PAL logic.

Figure 2.  shows the simplest Programmable Array Logic device with only two inputs. Inverted and non-inverted inputs (four inputs) are connected to the AND through fuses. Output from the AND is then directly connected to the OR gate. Any two input logic function can be realized using this device by burning off the unwanted fuses at the input of each AND gates.

Fig 2: Programmable Array Logic

For example consider an XOR gate. If the inputs are labeled as ‘A’ and ‘B’ then the output can be given by 

To implement this, we only need inputs A and B’ in the first (top) AND gate and A’ and B inputs in the second (bottom) AND gate. Rest two inputs in each AND gate is not needed, therefore, respective fuses are burned off. Two input XOR gates using Programmable Array Logic is shown below.

Fig 3. XOR gate Implementation using Programmable Array Logic

(c). Programmable Logic Array (PLA)

Programmable Logic Array or PLA  is used to implement logic functions in digital circuits. The structure has programmable AND-matrix, programmable OR-matrix, input and output buffers. Block diagram of a PLA device is as shown below.

Both inverted and original values of each PLA inputs are provided by input buffers. Input to both AND and OR gates are through fuse and therefore they can be burned off depending on our requirements. Structure of a PLA with all fuses (before programming) is shown below. 

Two input PLA structure can be used to realize any two input logic gates. For that, fuses which are not required to realize that particular logic function are burned off. For example, XOR gate realized using a programmable Logic device is shown below.

Characteristic equation of a XOR gate contains of two min terms. Given by 

Each AND is used to generate a particular min term and required min terms can be selected using the fuses in the input of OR gate.

(d). Generic Array Logic (GAL)

A GAL or Generic Array Logic device consists of a re-programmable PAL matrix and a programmable output-cell. GAL is an improved form of PAL which uses electrically erasable CMOS cells instead of fuses. Therefore, AND matrix of GAL can be re-programmed several times unlike one time programmable PAL devices.  AND matrix is followed by fixed OR matrix (inside output cell), used to sum off all min terms from the AND output. Block diagram of a GAL device is shown here.

Generic Array Logic

                                               Block of Generic Array Logic

Output Logic Macrocell

Another added feature of GAL is that it also has reprogrammable output logic called OLMC (Output Logic Macrocell).  Internal sturcture of an output cell is shown below.

As shown in the figure three main components of an output cell are:

(a). N-input OR,

(b). D-flip-flop,

(c). Multiplexers.

Like in PAL, OR gates are used to sum off min terms from the output of the AND gates. An OLMC cell consists of a D-flip-flop, which is used to implement sequential circuits. Multiplexers in the OLMC cells are used to select the routing of the input signals to the external output or to the feedback output. It is also used to select from the sequential and non-sequential output taken from the input and output of the D-flip-flop depending on the requirement.  

(e). Complex Programmable Logic Device (CPLD)

CPLD is defined as the network of PLDs that are connected together through a switching matrix. General block diagram of a CPLD is shown here. The global interconnection matrix, as shown in the figure, is reconfigurable and so we can change the connections between the Functional Blocks depending on our requirement.

Complex Programmable Logic Device

                                               Blocks of Complex Programmable Logic Device

Each Functional Block (FB) in the CPLD contains a re-programmable AND/OR array along with a bank of macro-cells. Therefore, multiple types of logic functions, both combinational and sequential circuits, can be implemented using CPLD. As shown in the figure, it is connected to the external world through the I/O blocks. The entire device contains thousands to tens of thousands of logic gates. Therefore, more complex designs, other than PLD devices, can be implemented using CPLD.

(f). Field-Programmable Gate Array (FPGA)

FPGA or Field Programmable Gate Array is now used in the mainstream of modern IC verification. Circuit design is done in Hardware Description Language, which is then synthesized to bit streams before burning into FPGA core. It can be used to realize simple digital logic gates to complex mathematical equations. 

Logic blocks in FPGA architecture are arranged in two dimensional arrays. Hierarchy of reconfigurable interconnects is then programmed to implement complex circuits. Desired logic function is implemented using this logic block, which is then connected together using programmable switch boxes. Figure shows, architecture of FPGA containing array of Logic blocks, interconnects, Switch blocks and I/O blocks.

Complex designs are first divided into small functions. Logic blocks are used to implement these sub functions and connections are made using programmable interconnects. The figure shows the architecture of programmed FPGA. Required sub functions are implemented using each logic blocks, which is then programmed and interconnected using switch boxes.

FPGA

Logic Block

Logic Blocks in the FPGA are used to implement sub functions. Any type of logic function (both combinational and sequential) circuits, can be implemented using a logic block. Therefore, logic blocks are commonly referred to as configurable logic blocks (CLBs). A basic Logic block contains

  • Lookup table (LUT): to implement the combinational logic functions.
  • Register (D flip flop): to store the output from the Lookup Table.
  • Multiplexer: to select the output from the LUT. 

A simple block diagram of a logic block consists of a lookup table, register and a multiplexer as shown in the figure. SRAM is used to implement lookup table. Therefore, desired logic function can be implemented by varying the data stored in the SRAM. Output from the lookup table is given as inputs to both multiplexer and D flip flop. D flip flop is used to delay the output. And depending on the application, the multiplexer selects LUT output or delayed output. Therefore, by using select input of the multiplexer we can implement both combinational and sequential circuits using logic blocks. Many such logic blocks are configured and finally interconnected using the switch box to build the desired complex circuits.     

Compared to other logic devices FPGA has very high logic density. Which means, a single FPGA chip contains ten thousand to eight million gates. Therefore, more complex logic circuits can be implemented using FPGA.  FPGA undergo concurrent processing which is faster and more efficient than other pipeline architectures.

After manufacturing, customer configures desired circuit in to FPGA. The main advantage of FPGA is its ability to reprogram. Therefore, it is mostly preferred during the design phase where continuous changes in the requirements can occur.  Whereas, Custom ICs are expensive, not programmable and takes long time to design. Disadvantages of FPGA are that, they are slow and they draw more power. The configuration of FPGA is stored in the RAM (volatile), so once they lose power its configuration is lost. Therefore in practical applications, configurations are externally stored in non-volatile flash memories and from there data is automatically restored after retaining the power.

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